1. Field of the Invention
The present invention relates to design layout formation and a mask data processing method for fabricating a semiconductor integrated circuit. More specifically, the present invention relates to a mask data processing method for optimizing a hierarchical structure.
2. Description of the Related Art
When shipping design data in semiconductor fabrication, various verifications are performed to confirm the correctness of the data.
For example, a design rule check is performed to verify whether design rules are satisfied. The design rules are basic design agreements determined on the basis of the device conditions and process conditions, and concerning the minimum dimension, space, shape, and the like.
Other examples are verifications using a difference check for checking whether a difference from previous data is produced in an unexpected portion, a shape check, circuit simulation, and process simulation.
Design data having passed these verifications is taped out as data from which no problem is detected by the regular test, and supplied to mask data processing.
On the other hand, as the semiconductor design rules become finer and the processes become complicated in recent years, the rules and contents of the mask data processing become more and more complicated in particularly critical layers that are very fine and have high process difficulties (e.g., Jpn. Pat. Appln. KOKAI Publication No. 2005-181524).
Examples are optical proximity correction, insertion of an auxiliary pattern equal to or smaller than a resolution limit, dummy pattern insertion, and shifter generation and placement of a phase shift mask. The load and calculation cost of the formation of the mask data processing rules keep on increasing.
In the verifications performed before design data to be supplied to the mask data processing is taped out, it is very difficult to predict the sizes of intermediate data/processed data in the mask data processing, and the process time of the mask data processing.
For example, even when design data is found to have a correct shape, if the hierarchical structure of this design data does not match the mask data processing tool, the process time or the intermediate data/processed data sizes may unexpectedly increase. This may cause a schedule delay or abnormal termination of the processing resulting from an insufficient data storage area.
When the cause of an inconvenience such as an abrupt increase in process time of the mask data processing is checked, it is sometimes found that the hierarchical structure of a memory cell array or the like is not held but expanded in hierarchical processing of the mask data processing. A memory cell array and its peripheral portion have very large numbers of repetitions. If the hierarchy is expanded, therefore, the data size enormously increases. Especially when a region such as a high-precision OPC (Optical Proximity Correction) region requiring a large calculation amount for processing is expanded, the calculation amount significantly increases. As a consequence, the process turn around time worsens.
An inconvenience caused by the hierarchical structure as described above is often overlooked because it hardly comes up to the surface even when design data of a very small region is checked through the mask data processing as a test. Therefore, the inconvenience reveals itself for the first time in the stage of the mask data processing. Correcting this inconvenience requires rearrangement of the process machine, rescheduling, and reformation and reverification of the design data, and these works require much labor and time. Especially when the hierarchical structure of the design data is manually corrected, the operation is very time-consuming, and errors readily occur. This further delays the schedule and increases the cost.
Also, the size of a fringe region in the hierarchical processing increases depending on the operation method of the mask data processing. The fringe region is a region for which a graphical operation is repetitively performed in order to take account of the surrounding layout, and which is discarded after that. If a portion corresponding to this fringe region includes a region such as a high-precision OPC region requiring a large calculation amount for processing, this processing requiring a large calculation amount is repetitively executed, so the process time increases.
In the fabrication of a semiconductor device, the increase in cost caused by the delay of the schedule is serious. That is, the machine resources must be given an excessive margin in order to hold an appropriate turn around time according to a predetermined schedule. Accordingly, the increase in cost in preparation for the infrastructure of the mask data processing increases the overall cost of the mask data processing.